物理設(shè)計(jì)崗位職責(zé)
芯片物理設(shè)計(jì)工程師九州華興集成電路設(shè)計(jì)(北京)有限公司九州華興集成電路設(shè)計(jì)(北京)有限公司,九州華興,九州華興WorkwithFrond-EnddesignteamandPhysicaldesignteamforlargescaleASICchipphysicalimplementation(HierarchicalDesign).Includetoplevelphysicalpartition,blocksizingandshaping,blockportassignment,powerplanning,top/blocklevelP&Rimplementation.
Workforprojecthighqualityandontimedelivery.
Responsibilities:
1.ResponsibleforVerilogtoGDSimplementation,powersignoff,areaEvaluation,Timingclosure,STA,Physicalverification
2.ExperiencedinEDAtools(e.g.Synopsys,Candence,Mentoretc)
3.Criticalissueresolveontopcongestionortimingissues.
4.Betterbeexpertononeormoreaspectlike:clocktreesynthesis/power/physicalverification.
SkillsandKnowledge:
1.Goodknowledgeforsynthesis,floorplan,place-and-route,timingclosure,DFM,DFT,poweranalysis,Signalintegrityanalysis,Hierarchicalflow
2.Goodatusingscriptprocessing.(TCL、Perl……)
3.Projecttapeoutexperienceisneeded
4.28nmandbeyond(advancednode)tapeoutexperienceisagoodplus.
5.Strongverbalcommunicationandinterpersonalskillstoworkcloselywithavarietyofindividual
6.Teamworkspirit
Qualifications
EducationandExperience
MSEEwith3+yearsorBachelorwith5+ofindustrialexperienceofdeepsubmicrondigitalASICdesign.
篇2:芯片物理設(shè)計(jì)工程師崗位職責(zé)芯片物理設(shè)計(jì)工程師職責(zé)任職要求
芯片物理設(shè)計(jì)工程師崗位職責(zé)
芯片物理設(shè)計(jì)工程師九州華興集成電路設(shè)計(jì)(北京)有限公司九州華興集成電路設(shè)計(jì)(北京)有限公司,九州華興WorkwithFrond-EnddesignteamandPhysicaldesignteamforlargescaleASICchipphysicalimplementation(HierarchicalDesign).Includetoplevelphysicalpartition,blocksizingandshaping,blockportassignment,powerplanning,top/blocklevelP&Rimplementation.
Workforprojecthighqualityandontimedelivery.
Responsibilities:
1.ResponsibleforVerilogtoGDSimplementation,powersignoff,areaEvaluation,Timingclosure,STA,Physicalverification
2.ExperiencedinEDAtools(e.g.Synopsys,Candence,Mentoretc)
3.Criticalissueresolveontopcongestionortimingissues.
4.Betterbeexpertononeormoreaspectlike:clocktreesynthesis/power/physicalverification.
SkillsandKnowledge:
1.Goodknowledgeforsynthesis,floorplan,place-and-route,timingclosure,DFM,DFT,poweranalysis,Signalintegrityanalysis,Hierarchicalflow
2.Goodatusingscriptprocessing.(TCL、Perl……)
3.Projecttapeoutexperienceisneeded
4.28nmandbeyond(advancednode)tapeoutexperienceisagoodplus.
5.Strongverbalcommunicationandinterpersonalskillstoworkcloselywithavarietyofindividual
6.Teamworkspirit
Qualifications
EducationandExperience
MSEEwith3+yearsorBachelorwith5+ofindustrialexperienceofdeepsubmicrondigitalASICdesign.
篇3:芯片物理設(shè)計(jì)崗位職責(zé)任職要求
芯片物理設(shè)計(jì)崗位職責(zé)
芯片物理設(shè)計(jì)工程師九州華興集成電路設(shè)計(jì)(北京)有限公司九州華興集成電路設(shè)計(jì)(北京)有限公司,九州華興WorkwithFrond-EnddesignteamandPhysicaldesignteamforlargescaleASICchipphysicalimplementation(HierarchicalDesign).Includetoplevelphysicalpartition,blocksizingandshaping,blockportassignment,powerplanning,top/blocklevelP&Rimplementation.
Workforprojecthighqualityandontimedelivery.
Responsibilities:
1.ResponsibleforVerilogtoGDSimplementation,powersignoff,areaEvaluation,Timingclosure,STA,Physicalverification
2.ExperiencedinEDAtools(e.g.Synopsys,Candence,Mentoretc)
3.Criticalissueresolveontopcongestionortimingissues.
4.Betterbeexpertononeormoreaspectlike:clocktreesynthesis/power/physicalverification.
SkillsandKnowledge:
1.Goodknowledgeforsynthesis,floorplan,place-and-route,timingclosure,DFM,DFT,poweranalysis,Signalintegrityanalysis,Hierarchicalflow
2.Goodatusingscriptprocessing.(TCL、Perl……)
3.Projecttapeoutexperienceisneeded
4.28nmandbeyond(advancednode)tapeoutexperienceisagoodplus.
5.Strongverbalcommunicationandinterpersonalskillstoworkcloselywithavarietyofindividual
6.Teamworkspirit
Qualifications
EducationandExperience
MSEEwith3+yearsorBachelorwith5+ofindustrialexperienceofdeepsubmicrondigitalASICdesign.